The present invention relates to a semiconductor device, a circuit board, and an electronic instrument.
In order to reduce the planar area of a semiconductor chip, it is known that a bump as an external electrode is caused to overlap a formation region of elements (transistor) (see Japanese Patent Application Laid-open No. 9-283525). An interconnect layer and an electrode pad above the interconnect layer are formed through an insulating layer on the formation region of the elements. The interconnect layer and the electrode pad are electrically connected through a contact section embedded in the insulating layer. A part of the electrode pad is open from a passivation film, and a part of the bump overlaps the opening. A barrier layer lies between the electrode pad and the bump in order to prevent diffusion between the electrode pad and the bump.
However, even if the barrier layer lies between the electrode pad and the bump, it is difficult to completely prevent diffusion between the electrode pad and the bump inside the opening in the passivation film depending on the thickness of the barrier layer and other conditions. In a related-art structure, since the contact section is connected with the electrode pad inside the opening in the passivation film, electrical connection reliability near the contact section may deteriorate if diffusion occurs to even only a small extent.
The thickness of the barrier layer is usually about 2000 to 5000 angstroms. If the thickness of the barrier layer is increased in order to prevent deterioration of the barrier performance, cost is increased. Therefore, it is desirable to increase the barrier performance without increasing the thickness of the barrier layer.